Area-Delay and Energy Efficient 2-D DWT Lifting VLSI Architecture for Higher Block Size Image | Original Article

ABSTRACT:

ABSTRACT

This paper analyzed the lifting and flipping discrete wavelet transform (DWT) data-path and proposed area delay and energy efficient lifting 2-D DWT VLSI architecture. Theoretical estimate shows that the critical-path-delay (CPD) of lifting cell is higher by 10 AND, OR and Invert (AOI) gates when scaling operations of separated two-dimensional (2-D) DWT are integrated and performed in single step then lifting-based 2-D DWT involves half the number of scaling constants than the flipping-based 2-D DWT. Large number of multipliers are saved into significant saving in multipliers when lifting 2-D DWT is implemented  using massively in a parallel structure with integrated scaling. We have derived full-parallel lifting-based 1-level 2-D DWT structure involves M/2 number of less multipliers than the flipping-based 2-D DWT structure.  ASIC synthesis result shows that proposed lifting-based structure involve nearly 8% less ADP and 22.5% less EPI than the proposed flipping-based structures on average for block sizes 16 and 32. Compared with the existing lifting-based structure, the proposed lifting-based structures involve 29% less ADP, and 44% less EPI for block size 32, respectively. Compared with existing flipping-based structure, the proposed lifting-based and flipping-based structures, respectively, involve 6.4 times, 5.8 times as little as ADP, and 3.8 times, 2 times as little as EPI for block-sizes 32.The flipping scheme only offers area-delay efficient 2-D DWT structures for smaller block sizes less than 4, where lifting-scheme offers area-delay efficient 2-D DWT structures for block size higher than 4.